1. Field of the Invention
The present invention relates to a technology for supporting verification operation in large-scale integration (LSI) designing.
2. Description of the Related Art
In LSI designing, it has conventionally been demanded to improve work efficiency to supply competitive products to the market as early as possible by shortening the design period. On the other hand, verification operation in the design period is indispensable to verify whether the LSI works properly. Especially for an LSI requested to be large in scale, high in performance and speed, and low in power consumption, the verification operation is important to maintain high quality of the LSI.
Conventional verification conducted in a design period will be explained. If one LSI is developed, a successive LSI may be developed by improving the developed LSI (previous LSI). A difference between the successive LSI and the previous LSI is only a part of the circuit and the remaining parts are in common. Generally, in verification of an entire LSI, various tests to verify logics are provided to test the LSI. Therefore, when verifying the entire successive LSI, it is a common practice to reuse the tests conducted on the previous LSI. Specifically, all of the tests conducted on the previous LSI, or some necessary tests selected based on experience of a designer are conducted on the successive LSI. Moreover, a program structure of the successive LSI is analyzed and tests relating to improved parts may be selected to be conducted on the previous LSI.
However, because the LSI is formed in large scale and to have high performance as described above, the number of tests conducted on the previous LSI is enormous. Therefore, verification operation takes long time, and this leads to long design period. In addition, if the verification operation is performed based on experience of a designer, unnecessary tests can be selected to be included in the tests conducted on the successive LSI. Thus, the time necessary for verification operation increases, and as a result, the design period becomes longer. If the verification operation is performed analyzing the program structure of the successive LSI, only required tests can be selected. However, analysis of the program structure takes time. This also results in long design period.